Microelectromechanical systems (MEMS) are small integrated devices or systems that combine electrical and mechanical components. The components can range in size from the sub-micrometer level to the millimeter level, and there can be any number, from one, to few, to potentially thousands or millions, in a particular system. Historically MEMS devices have leveraged and extended the fabrication techniques developed for the silicon integrated circuit industry, namely lithography, doping, deposition, etching, etc. to add mechanical elements such as beams, gears, diaphragms, and springs to silicon circuits either as discrete devices or in combination with integrated silicon electronics. Whilst the majority of development work has focused on silicon electronics additional benefits may be derived from integrating MEMS devices onto other existing electronics platforms such as silicon germanium (SiGe), gallium arsenide and, indium phosphide for RF circuits and future potential electronics platforms such as organic based electronics, nanocrystals, etc.
In the field of radio frequency integrated circuits (RFIC), microelectromechanical systems (MEMS) are currently gaining momentum. The current design trend leans towards system-on-chip (SOC) implementations in which electronics and MEMS are integrated on a single die. For RF applications, high quality filters and resonators must typically be implemented as bulky off-chip surface-acoustic wave (SAW) filters to achieve a satisfactory quality factor (Q-factor). However, current advances in MEMS technology make it possible to implement such elements on-chip with a comparable Q-factor, provided proper packaging is available. The Q-factor of a MEMS resonating device is strongly dependent on the level of vacuum in its environment. Indeed, reduced pressure minimizes air resistance, resulting in smaller damping of the mechanical structure's vibration.
Additionally, and beneficially, MEMS device applications today also include inkjet-printer cartridges, accelerometers, miniature robots, micro-engines, locks, inertial sensors, micro-drives, micro-mirrors, micro actuators, optical scanners, fluid pumps, transducers, chemical sensors, pressure sensors, and flow sensors. New applications are emerging as the existing technology is applied to the miniaturization and integration of conventional devices. These systems can sense, control, and activate mechanical processes on the micro scale, and function individually or in arrays to generate effects on the macro scale. The micro fabrication technology enables fabrication of large arrays of devices, which individually perform simple tasks, or in combination can accomplish complicated functions.
MEMS have become a successful sensing and actuating technology. Because of their extensive optical, electrical to mechanical functionalities, MEMS devices are suited to applications in many different fields of science and engineering. However, because of this vast range of functionality, MEMS fabrication processes, unlike the microelectronics industry, are difficult to gear towards general applications. As a result, most processes are aimed at the fabrication of a few devices, and usually performance of the devices is hindered by process variability. As MEMS devices are typically sensing weak analog signals, for example pressure, acceleration, vibration, magnetic or electric fields, with capacitive based elements, there is considerable benefit in being able to integrate analog front-end electronics to buffer, amplify and process these weak electronic signals and either facilitate their direct processing, such as with RF signals, or their digitization for sensing and measurements applications.
Chip Level Packaging and Wafer Level Packaging
Consequently, packaging of the MEMS is of critical importance, since it must ensure a stable high-vacuum environment. Vacuum packaging is usually performed at the chip level, meaning that each chip is individually enclosed in a hermetic package which is sealed with vacuum inside. For all its widespread use, chip-level packaging (CLP) presents significant drawbacks that make it particularly costly, including:                1) Very expensive hermetically sealable packages are required.        2) The chips must be encapsulated individually rather than by means of a batch process. This lengthens the production time of the system, thereby increasing costs.        3) The fragile MEMS devices are not protected during dicing and wire bonding, which has a negative impact on the yield, thus incurring greater costs.        
In fact, the costs of using CLP for hermetical packaging can exceed any other costs involved in the design of a MEMS system. As such it would be beneficial to replace CLP with a wafer-level packaging (WLP) process, particularly applications requiring very low pressure or vacuum environments around the MEMS device such as resonators. Whilst a WLP process is more complex to develop than CLP, it does present various worthwhile advantages because it allows batch encapsulation at the wafer scale. With WLP, the encapsulation of MEMS devices effectively becomes part of the micro-fabrication cycle rather than a post-process operation, i.e. the different chips on a wafer do not need to be enclosed individually, particularly in a vacuum, because they are all processed simultaneously. This makes such a WLP process more efficient as well as cheaper for mass production. After the WLP process is complete, the encapsulated chips can still be packaged in a conventional manner. However, the external package is neither responsible for hermetically preserving a vacuum environment nor ensuring the fine mechanical protection of the MEMS devices: all this is performed by the WLP encapsulation. The only potential purpose of this package (if used at all) is to provide an electrical interface and coarse mechanical protection. Hence, inexpensive standard packages can be used instead of customized CLP solutions. Alternatively, an attractive option is to surface mount the WLP-encapsulated MEMS chip directly to the PCB, totally circumventing the need for an external package, an option which is not available with CLP.
Further with WLP, because the MEMS are protected at an earlier stage of the micro-fabrication cycle, the overall processing yield is improved, thereby lowering cost. Indeed, the released devices are encapsulated before the chips are even diced, which prevents the fragile structures from being damaged by dust and debris. Furthermore, this WLP process is advantageous in terms of testability. Indeed, MEMS devices requiring vacuum to operate satisfactorily must be encapsulated before electrical testing can be performed. With CLP, expensive enclosures are wasted to test faulty devices, since each die must be fully packaged before it can be verified. On the other hand, WLP allows devices to be tested at the wafer-level using a probe station without the need for any test fixture, since the devices are already encapsulated in vacuum before dicing. Therefore, malfunctioning devices can be conveniently singled out, so that only the operational devices are further processed.
It would be beneficial for the WLP process to minimize the processing temperatures involved, in the goal of allowing maximal compatibility with a large number of custom MEMS processes, even if metal interconnects with a low melting point are present, as well as allowing the WLP process to package devices requiring low processing temperatures from the presence of CMOS electronics. Such an overall low temperature process providing a route to system-on-chip implementations.
Low Temperature Ceramic MEMS Materials
Within the prior art the vast majority of research and current commercial products has been undertaken on silicon due to the availability of a manufacturing and process infrastructure from electronics However, the mechanical properties of silicon do not make it the most suitable structural material for MEMS. Recently, silicon carbide (SiC) has generated much interest as a MEMS structural material because of its distinctive properties. SiC offers improved mechanical properties such as higher acoustic velocity, high fracture strength and desirable tribological properties. Its ability to sustain higher temperatures, and resist corrosive and erosive materials makes SiC, unlike conventional silicon which is employed in CMOS electronics as the substrate material. As such SiC offers potential as a candidate material for use in harsh environments. These factors, along with the maturation of deposition techniques, make SiC a potential choice for high-performance MEMS processing.
However, difficulties with SiC processing have made its use non-trivial as it is non-conductive and difficult to deposit and dope at temperatures compatible with CMOS electronics. Stress control is also difficult because of the high intrinsic stresses that can develop in such a material. Because of its intrinsic inertness, selective etching of SiC is difficult. As most materials are etched at a faster rate than SiC, issues arise when masking SiC for patterning and ensuring a reliable etch-stop. Whether it is for doping or for deposition, SiC needs to generally be processed at high temperatures. As such prior art SiC MEMS processes have not lent themselves well to CMOS integration. Further as most MEMS applications require electrical signal processing, integration of MEMS to transistor-able processes, such as CMOS, is paramount.
As outlined in U.S. patent application Ser. No. 12/341,013 filed Dec. 21, 2008 “Low Temperature Ceramic Microelectromechanical Structures” by F. Nabki and T. Dusatko, a low temperature silicon-carbide MEMS manufacturing process is taught. The processes providing for MEMS manufacturing processes with maximum temperatures below 350° C., and even 250° C. Therefore, it would be beneficial to have a WLP packaging process for these MEMS processed devices that allows for manufacturability and integration of SiC with silicon CMOS electronics to be sustained and thereby effectively harness the benefits of SiC.
Further, the WLP packaging process as will be described with respect to different exemplary embodiments of the invention are not limited to a single application and can be applied to a vast number of surface-micromachining MEMS processes, materials, and device designs. The benefit of compatibility with the low temperature SiC processes for direct MEMS integration also allows its use with more conventional MEMS processes at substantially higher temperatures.
Electrical Interconnection and Mechanical Integrity
Within CMOS electronics, it is common to employ vertical feed-throughs that are beneficially employed through the whole thickness of the silicon substrate wafer. This creates a direct electrical contact from the lower side of the silicon wafer to the encapsulated MEMS. This beneficially removes the requirement for MEMS electrical interconnections to the outside of the cavity on the same upper side of the silicon wafer. Such an interconnection that would traverse through the wafer bonding interface between the silicon substrate and the cover wafer providing the hermetic seal, and cause topography and sealing issues. Accordingly, vertical feed-throughs improve the quality of the bond by eliminating irregularities, thereby improving the encapsulation hermeticity and yield. Furthermore, the interconnect parasitics are reduced by such an interconnection scheme.
Further such vertical feed-throughs beneficially allow the electrical contacts to be on the lower side of the substrate, allowing the chips to be directly mounted to a PCB or to another semiconductor chip. When mounted, the devices still face the upward orientation, which is particularly beneficial for devices providing sensing functionality requiring access to the upper surface of the MEMS by gas or liquid flow, as well as those addressing optical applications i.e. micro-optical-electromechanical systems (MOEMS) because light can reach the MEMS directly from above.
However, the provisioning of vertical feed-throughs through the thickness of the substrate provides two drawbacks within the prior art. Firstly, the inner surfaces of the vertical feed-through are coated with a thin layer of metallization to provide the contact path from the upper surface to the lower surface. Such thin metallizations toward the narrower apex of the vertical feed-throughs form sealing membranes of the overall packaged silicon circuit and MEMS structure. Such membranes form one potential point of failure for the packaged component due to rupturing, gas transport, etc.
Secondly the removal of large portions of the silicon substrate beneath the MEMS device results in a weakening of the mechanical integrity and impacts the performance of the MEMS device. Accordingly it would be beneficial to provide a reinforcement of the sealing membranes and silicon substrate with the in-filling of the vertical feed-through structures with a material providing mechanical integrity that is compatible with the overall process flow in respect of material parameters, processing temperature etc. Also, it would be beneficial to provide a method to create these membranes with fine resolution and accuracy to reduce their size, and hence minimally affect the MEMS mechanical integrity and performance. This is accomplished by the use of anisotropic etching and precise alignment methods.
It would therefore be beneficial to provide a method of processing and packaging MEMS devices that allows for their encapsulation in a wafer level process. It would be further beneficial for the method to be compatible with low temperature processing for MEMS devices fabricated directly onto CMOS electronics. Additionally benefit would be further achieved if the method supported provisioning of through-wafer electrical interconnects with improved mechanical integrity and improved performance as a barrier to high pressure differentials where the encapsulated MEMS is either under low pressure, vacuum, or pressurized.